@MASTERSTHESIS{ 2017:1192079181,
 	title = {Development of a test methodology for FinFET-Based SRAMs},
 	year = {2017},
 	url = "http://tede2.pucrs.br/tede2/handle/tede/7647",
 	abstract = "Miniaturization has been the industry’s main goal over the last few years,
 as it brings benefits such as high performance and on-chip integration as well as
 power consumption reduction. Alongside the constant scale-down of Integrated Circuits
 (ICs) technology, the increasing need to store more and more information has
 resulted in the fact that Static Random Access Memories (SRAMs) occupy great
 part of Systems-on-Chip (SoCs).
 The constant evolution of nanotechnology brought many revolutions to semiconductors,
 making it also necessary to improve the integrated circuit manufacturing
 process. Therefore, the use of new, complex processing steps, materials, and
 technology has become necessary.
 The technology-shrinking objective adopted by the semiconductor industry
 promoted research for technologies to replace CMOS transistors. FinFET transistors,
 due to their superior electrical properties, have emerged as the technology most
 probably to be adopted by the industry.
 However, one of the most critical downsides of technology scaling is related
 to the non-determinism of device’s electrical parameters due to process variation.
 Miniaturization has led to the development of new types of manufacturing defects
 that may affect IC reliability and cause yield loss.
 With the production of FinFET-based memories, there is a concern regarding
 embedded memory test and repair, because fault models and test algorithms
 used for memories based on conventional planar technology may not be sufficient
 to cover all possible defects in multi-gate memories. New faults that are specific to
 FinFETs may exist, therefore, current test solutions, which rely on operations executing
 specific patterns and other stressing conditions, may not stand to be reliable
 tools for investigating those faults.
 In this context, this work proposes a hardware-based methodology for testing
 memories implemented using FinFET technology that monitors aspects of the
 memory array and creates output signals deriving from the behavior of these characteristics.
 Sensors monitor the circuit’s parameters and upon changes from their
 idle values, create pulses that represent such variations. These pulses are modulated
 applying the pulse width modulation techniques. As resistive defects alter current
 consumption and bit line voltages, cells affected by resistive defects present altered
 modulated signals, validating the proposed methodology and allowing the detection
 of these defects. This further allows to increase the yield after manufacturing
 and circuit reliability during its lifetime. Considering how FinFET technology has
 evolved and the likelihood that ordinary applications will employ FinFET-based
 circuits in the future, the development of techniques to ensure circuit reliability has
 become a major concern.
 The presented hardware-based methodology, which was implemented using
 On-Chip Sensors, has been divided in two approaches: monitoring current consumption
 and monitoring the voltage level of bit lines. Each approach has been validated
 by injecting a total of 12 resistive defects, and evaluated considering different operation
 temperatures and the impact of process variation.",
 	publisher = {Pontifícia Universidade Católica do Rio Grande do Sul},
 	scholl = {Programa de Pós-Graduação em Engenharia Elétrica},
 	note = {Faculdade de Engenharia}
}