@MASTERSTHESIS{ 2020:693515801,
 	title = {A hardware-based approach to guarantee critical task schedulability in TDMA bus access of multi-core architecture},
 	year = {2020},
 	url = "http://tede2.pucrs.br/tede2/handle/tede/9694",
 	abstract = "The use of multi-core processors in general-purpose real-time embedded systems has experienced a considerable increase in recent years. Unfortunately, critical applications such as those devoted to aerospace and automotive, for instance, are not benefiting from the high-performance of this type of processor. The major obstacle: we may not predict and provide any guarantee on real-time properties of software running on such platforms. Shared memory bus is the main source of timing unpredictability due to access contention among cores. In these applications, when a critical task is executed, all other ordinary (non-critical) tasks are temporarily paused until completing the critical task. The present work aims to counteract with this problem. Hereafter, we propose an approach aiming to guarantee the complete execution of a critical task, i.e., preventing critical task execution from violating deadline while running in a multi-core platform. We assume that the system is simultaneously running the critical task in the Critical Core, and any number of (non-critical)
 tasks in the remaining cores of the system, with a mixed-criticality profile. The proposed approach is based on the implementation of a watchdog (namely, Shared Bus-Access Controller: SBAC) that is connected to the address bus between the processor and the system memory. Though, by monitoring the memory address bus of the system, the watchdog is able to predict the event of critical task execution violation. The approach assumes that bus access is based on the Time-Division Multiplexing Access (TDMA) policy, which allocates time slices for each of the cores to access the system bus. In this context, a time slice is of fixed size.To fit critical task execution into the deadline, a different number of time slices is allocated to each task running in
 the system. To validate the approach, the watchdog was implemented in VHDL language and connected to a dual-core version of the LEON 3 soft-core processor. The whole system was simulated on ModelSim and prototyped into a commercial FPGA. Practical experiments have shown that the proposed technique effectively guarantees a smooth execution of a critical task simultaneously with other non-critical tasks on a multi-core platform.",
 	publisher = {Pontifícia Universidade Católica do Rio Grande do Sul},
 	scholl = {Programa de Pós-Graduação em Engenharia Elétrica},
 	note = {Escola Politécnica}
}