Modelagem e projeto de um gerador de relógio local baseado em DCO para MPSoCs GALS

Abstract

Currently, the use of multiprocessor systems on chip or MPSoCs are a trend in the electronic industry. Increasing numbers of processors and other Intellectual Property Cores (IP Cores) are integrated, which enable massive parallel processing, and allow achieving devices with increased performance. This trend to employ MPSoCs is driven, among other factors, by advances in networks on chip research, due to their higher scalability, when compared to other types of interconnection architectures. On the other hand, there is a growing demand for portable devices, with fierce competition for market shares of smartphones, tablets and ultrabooks, among other devices. However, increased performance in these devices leads to greater energy consumption. Such high consumption rates become a serious problem, because mobile platforms have limited amounts of energy available for immediate use. Therefore, the research of design techniques aimed at energy savings becomes relevant, once the evolution of energy source characteristics does not follow the evolution of electronic devices. Because a considerable amount of energy consumption in synchronous circuits is required for the generation, distribution and maintenance of the clock signal, this work capitalizes on the use of design techniques that avoid employing global clocks. One option to this consists in partitioning a complex electronic system into a set of synchronous modules that communicate asynchronously, in what are called globally asynchronous locally synchronous (GALS) systems. This Dissertation describes a proposal and the detailed design of a local clock generator circuit, which allows to produce and control the operating frequency of each module in a GALS system, the so called processing elements (PEs). This generator provides a mechanism for dynamically changing the module operating frequency (dynamic frequency scaling or DFS), which makes it able to save energy through the elimination of global clock distribution trees, as well as enabling localized reduction of the frequency of modules subject to reduced instantaneous computational demand. The generator was designed in a 65 nm technology from STMicroelectronics. Results from preliminary design evaluation show that the proposed circuit dissipates only 0,058 μW of static power and presents an average dynamic power dissipation around 159 μW. The area taken by the clock generator control circuit is 0,0024 mm2. This represents an area overhead which is only 5% of the area of a minimalist network on chip router. Such results indicate the feasibility of using the proposed generator for driving relatively small MPSoC modules. Thus, the work especially contributes to consolidate the viability of GALS systems.