Uma exploração do espaço de projeto de processadores com hardware de ponto flutuante em FPGAS

Abstract

Arithmetic circuits are a fundamental part of digital systems, since every piece of information processed by them must first be encoded as numbers, and arithmetic is the ultimate way to systematically manipulate numbers. There exists a large number of available number encoding schemes, but three of these stand as useful in most situations: unsigned, integer and floating point. The first two are simpler and more universal, but some applications do require the recourse to the extended range of values, and the increased precision of floating point representations. Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This work describes the design process, the implementation and a preliminary evaluation of single-precision floating point hardware units for an instance of the MIPS processor architecture. It explores several fully-fledged implementations that have the form of strongly coupled coprocessors. These coprocessors take as little room as 4% of a medium-sized FPGA, while the processor CPU may take only 3% of the same device. The space exploration process described here values area, performance and power metrics and considers variations on the choice of synthesis tool, floating point unit generation method and architectural issues such as clocking schemes. The conducted experiments show reductions of more than 20 times in clock cycles count for typical floating point application modules, when compared to the use of software-emulated floating point processing.